Introduction
A single mistake in your schematic can cost you weeks of debugging time and hundreds of dollars in PCB respins. Whether it's a missing pull-up resistor, incorrect voltage rating, or forgotten decoupling capacitor, schematic errors have a way of surviving all the way to production if not caught early.
This comprehensive checklist consolidates wisdom from industry standards (IPC-2612, IEEE 315), manufacturer guidelines (Altium, Cadence, EMA Design), and real-world engineering experience into a single, actionable resource. With over 100 verification items organized into 10 categories, this checklist will help you catch errors before they become expensive mistakes.
Bookmark this page - You'll want to reference it before every design review.
Why Checklists Matter
The aviation and medical industries have long known what electronics engineers are now discovering: checklists save lives (and designs). Studies show that systematic checklist usage reduces errors by up to 35% in complex engineering tasks.
$5,000+
Average cost of a PCB respin
4-8 weeks
Typical delay per respin
85%
Errors catchable at schematic stage
Most PCB errors originate in the schematic phase. By investing 2-3 hours in a thorough schematic review, you can prevent issues that would take days or weeks to debug on a physical board.
How to Use This Checklist
Recommended Review Process
- First Pass (Self-Review): Go through all categories yourself before involving others
- Second Pass (Peer Review): Have a colleague review with fresh eyes
- Third Pass (Specialist Review): For complex designs, involve domain experts (power, RF, firmware)
- Sign-Off: Document who reviewed what, and any exceptions/waivers
Standard item
Critical item (must not skip)
Items marked as Critical are the most common sources of board failures and should never be skipped, even under time pressure.
Quick Reference Card
For quick pre-layout checks, focus on these top 10 most critical items:
Top 10 Critical Checks
- 1Decoupling capacitors on every IC power pin
- 2All symbol pin numbers verified against datasheets
- 3Pull-up/down resistors on all open-drain outputs
- 4Voltage regulator stability verified (load caps, ESR)
- 5Reset pins have external pull-up with RC filter
- 6Boot/strap pins configured correctly
- 7ESD protection on all external interfaces
- 8Polarized components identified (caps, diodes)
- 9UART TX/RX and SPI MOSI/MISO correctly crossed
- 10Design passes DRC/ERC with no unresolved errors
1Schematic Setup & Documentation
Template & Title Block
- CheckboxCorrect template applied to all schematic sheets
- CheckboxTitle block filled out completely (project name, revision, date, engineer)
- CheckboxCompany/organization name and logo present
- CheckboxDrawing number or document ID assigned
- CheckboxAll sheets same size for consistency
- CheckboxSheet sizes printable on standard office printers (Tabloid/A3 max)
Sheet Organization
- CheckboxTop-level sheet shows system block diagram and inter-sheet connections
- CheckboxTable of contents included for designs with 5+ sheets
- CheckboxLogical signal flow: inputs left, outputs right, power top, ground bottom
- CheckboxRelated functions grouped on same sheet
- CheckboxMulti-channel designs use hierarchical sheets
- CheckboxSheet numbering sequential and consistent
Version Control
- CheckboxRevision number incremented from previous releaseCritical
- CheckboxChange/revision log maintained with descriptions
- CheckboxDate of latest revision recorded
- CheckboxPrevious revisions archived and accessible
- CheckboxSchematic files in source control (Git, SVN)
Drafting Standards
- CheckboxNo 4-way wire junctions (use offset T-junctions)Critical
- CheckboxJunction dots clearly visible at all wire connections
- CheckboxCrossing wires without dots clearly not connected
- CheckboxComponents aligned to grid
- CheckboxWire connections properly snapped to component pins
- CheckboxNet labels used for improved readability vs long wires
- CheckboxPower and ground symbols used consistently
- CheckboxDifferential pairs labeled with _P/_N suffix
- CheckboxActive-low signals marked consistently (overbar or _N suffix)
2Power Supply Design
Input Power Protection
- CheckboxReverse polarity protection (diode, P-FET, or ideal diode IC)Critical
- CheckboxInput fuse or PTC resettable fuse sized correctlyCritical
- CheckboxTVS diode at power input for surge protection
- CheckboxInrush current limiter for high-capacitance systems
- CheckboxInput voltage range specified and verified against components
- CheckboxUnder-voltage lockout (UVLO) considered if needed
- CheckboxOver-voltage protection for sensitive downstream components
Voltage Regulators
- CheckboxOutput voltage accuracy meets requirements of connected ICsCritical
- CheckboxCurrent rating exceeds maximum load with margin (20%+ recommended)Critical
- CheckboxThermal dissipation calculated and acceptableCritical
- CheckboxInput voltage range verified against regulator specifications
- CheckboxEnable pin properly controlled or tied high/low
- CheckboxSoft-start configuration verified if available
- CheckboxFeedback resistor divider values calculated and verified
- CheckboxCompensation network designed for stability (if external)
- CheckboxLinear regulator dropout voltage acceptable at minimum input
- CheckboxSwitching regulator simulated for stability across load range
- CheckboxOutput capacitor ESR within regulator requirements
Decoupling & Filtering
- CheckboxEvery IC power pin has decoupling capacitorCritical
- CheckboxBulk capacitance at power supply outputsCritical
- CheckboxDecoupling values per manufacturer recommendations
- CheckboxCeramic capacitor DC bias derating considered (X5R, X7R)
- CheckboxFerrite beads used on sensitive analog power rails
- CheckboxSeparate analog and digital supply filtering
- CheckboxLow-ESR capacitors specified for high-frequency decoupling
Power Distribution
- CheckboxTotal power budget calculated and verified
- CheckboxAll ICs receive correct voltage rail
- CheckboxPower rail naming consistent throughout schematic
- CheckboxNet classes assigned for power traces (width requirements)
- CheckboxCurrent path from supply to load verified
- CheckboxBattery charging circuit isolated from main power path
Power Sequencing
- CheckboxMulti-rail sequencing requirements verified against IC datasheets
- CheckboxReset supervisor ICs used where soft-start timing is critical
- CheckboxEnable pins daisy-chained for sequential power-up if needed
- CheckboxPower-good signals monitored where available
3Signal Integrity
Digital Signals
- CheckboxLogic levels compatible between connected ICsCritical
- CheckboxPull-ups on all open-drain/open-collector outputsCritical
- CheckboxLevel shifters used where voltage domains differ
- CheckboxUnused inputs tied to appropriate logic level (not floating)
- CheckboxSeries termination resistors on fast edges (>10MHz)
- CheckboxParallel termination at end of transmission lines if needed
- CheckboxCritical timing signals have defined rise/fall time constraints
Analog Signals
- CheckboxADC inputs have anti-aliasing RC filter
- CheckboxOp-amp feedback polarity verified (negative feedback for amplifiers)
- CheckboxOp-amp input bias current paths provided
- CheckboxVoltage dividers calculated for accuracy under load
- CheckboxReference voltage precision meets system requirements
- CheckboxAnalog signal paths separated from digital noise sources
- CheckboxGuard rings or shields on high-impedance nodes if needed
Clocks & Oscillators
- CheckboxCrystal load capacitors match crystal specificationCritical
- CheckboxOscillator jitter/phase noise meets timing requirements
- CheckboxClock frequency tolerance verified for communication protocols
- CheckboxSeries termination resistor on oscillator output if needed
- CheckboxExternal crystals only used with integrated crystal oscillator circuits
- CheckboxClock distribution fan-out and loading verified
High-Speed Signals
- CheckboxDifferential pairs identified and marked in schematic
- CheckboxAC coupling capacitors on gigabit transceivers
- CheckboxDifferential pair polarity verified (_P to _P, _N to _N)
- CheckboxImpedance targets noted for layout (50Ω, 90Ω diff, etc.)
- CheckboxLength matching requirements documented
- CheckboxRF component frequency response verified across operating range
4Component Verification
Passive Components (R, C, L)
- CheckboxResistor power ratings verified (P = I²R or V²/R)Critical
- CheckboxCapacitor voltage ratings at least 50% above max applied voltageCritical
- CheckboxTantalum capacitors derated to 50% of rated voltageCritical
- CheckboxPolarized capacitors have correct polarity in schematicCritical
- CheckboxCeramic capacitor dielectric type specified (C0G, X5R, X7R)
- CheckboxResistor tolerance specified where precision matters
- CheckboxHigh-voltage resistors rated for applied voltage
- CheckboxInductor saturation current exceeds peak operating current
- CheckboxInductor DC resistance acceptable for power efficiency
- CheckboxFerrite bead impedance specified at relevant frequency
Active Components (ICs, Transistors)
- CheckboxSymbol pin numbers verified against datasheetCritical
- CheckboxPackage/footprint matches schematic symbolCritical
- CheckboxThermal pads connected to correct power rail (GND usually)Critical
- CheckboxAll IC power and ground pins connected
- CheckboxUnused IC sections/gates properly terminated
- CheckboxMOSFET gate resistors prevent oscillation
- CheckboxMOSFET gate-source voltage within absolute maximum
- CheckboxBJT base resistors limit base current appropriately
- CheckboxTransistor safe operating area (SOA) verified
- CheckboxDiode forward voltage drop acceptable in application
- CheckboxDiode reverse voltage rating exceeds maximum reverse voltage
- CheckboxLED current-limiting resistor calculated correctly
- CheckboxOptocoupler CTR degradation accounted for in design
Connectors
- CheckboxConnector pinout matches mating connector/cableCritical
- CheckboxStraight-through vs crossover cable requirements documented
- CheckboxPower pins rated for expected current
- CheckboxShield/drain pins connected appropriately
- CheckboxHot-plug capability considered if needed
- CheckboxMechanical keying prevents incorrect mating
- CheckboxConnector voltage ratings verified
- CheckboxSignal pins have defined state when disconnected (pull-ups/downs)
Mechanical Components
- CheckboxMounting holes and standoffs included
- CheckboxTest point accessibility verified
- CheckboxHeatsink mounting provisions included where needed
- CheckboxKeep-out areas for tall components documented
5Microcontroller & FPGA
MCU Power & Reset
- CheckboxAll VDD and VSS pins connected with individual decouplingCritical
- CheckboxReset pin has external pull-up (typ. 10kΩ) and filter capacitorCritical
- CheckboxReset supervisor IC used for reliable power-on resetCritical
- CheckboxVDDA/VSSA connected with additional filtering
- CheckboxVBAT connected to battery or tied to VDD
- CheckboxPower supply meets MCU requirements (ripple, accuracy)
- CheckboxBrown-out detection enabled and threshold set correctly
GPIO Configuration
- CheckboxBoot mode / strap pins configured for normal operationCritical
- CheckboxBoot pins accessible for alternate boot modesCritical
- CheckboxGPIO voltage levels compatible with connected devices
- Checkbox5V-tolerant pins used where needed (or level shifters added)
- CheckboxUnused pins configured as outputs low or inputs with pull-down
- CheckboxPin-sharing constraints verified (one peripheral per pin)
- CheckboxDMA channel conflicts avoided
- CheckboxTimer/PWM assignments don't conflict
Communication Buses
- CheckboxUART TX connects to RX of other device and vice versaCritical
- CheckboxI2C has pull-ups on SDA and SCL (typically 2.2kΩ-10kΩ)Critical
- CheckboxSPI MOSI/MISO/CLK correctly connected (master to slave)Critical
- CheckboxI2C addresses unique on each bus (no conflicts)
- CheckboxI2C pull-up value appropriate for bus speed and capacitance
- CheckboxSPI chip selects active-low with pull-ups for default deselect
- CheckboxCAN bus has termination resistors at both ends (120Ω each)
- CheckboxRS-485 has termination and bias resistors as needed
- CheckboxUSB data lines have required series resistors (if any)
- CheckboxUSB VBUS sensing implemented correctly
Programming & Debug
- CheckboxProgramming header accessible (JTAG, SWD, ISP)Critical
- CheckboxDebug interface powered in low-power modes
- CheckboxProgramming header pinout matches programmer
- CheckboxBoot/config flash provided for FPGAs and MPUs
- CheckboxFPGA I/O banking rules verified
- CheckboxFPGA clock inputs on clock-capable pins
- CheckboxMGT reference clocks meet jitter requirements
- CheckboxSTM32: JTRST not used as GPIO (errata consideration)
6Protection & Safety
ESD Protection
- CheckboxTVS diodes on all external connectorsCritical
- CheckboxESD protection on USB data linesCritical
- CheckboxESD protection on Ethernet data lines
- CheckboxUser-accessible buttons/switches have ESD protection
- CheckboxExposed metal (enclosure, heatsinks) properly grounded
- CheckboxTVS clamping voltage below IC absolute maximum ratings
- CheckboxTVS capacitance acceptable for high-speed signals
Overvoltage Protection
- CheckboxInput power has overvoltage protection (TVS, crowbar, or OVP IC)
- CheckboxOutputs protected against back-drive from connected equipment
- CheckboxFlyback/clamping diodes on inductive loads (relays, motors, solenoids)
- CheckboxSnubber circuits on switching nodes if needed
- CheckboxMOSFET drain-source voltage rating exceeds transients
Overcurrent Protection
- CheckboxInput fuse appropriately rated (I²t, voltage, interrupt rating)Critical
- CheckboxOutput current limiting on power outputs
- CheckboxShort-circuit protection on voltage rails with external connections
- CheckboxLoad switches with current limiting for hot-plug applications
- CheckboxPTC resettable fuses sized for operating and fault currents
Thermal Protection
- CheckboxThermal shutdown on voltage regulators enabled (if available)
- CheckboxTemperature monitoring for high-power components
- CheckboxHeatsink thermal resistance calculated and acceptable
- CheckboxThermal vias planned for power components
- CheckboxAmbient temperature derating considered
7Testability & Debug
Test Points
- CheckboxTest point on each power railCritical
- CheckboxMultiple ground test points for scope probe clips
- CheckboxTest points on critical analog signals
- CheckboxTest points accessible for oscilloscope probes
- CheckboxCurrent-sense test points for power measurements
- CheckboxDedicated ground near analog test points
Debug Access
- CheckboxDebug connector accessible without disassemblyCritical
- CheckboxSerial console (UART) pins available for debugging
- CheckboxSWO/ETM trace pins exposed if needed
- CheckboxDebug GPIOs reserved for development
- Checkbox0Ω resistors on strap pins for easy rework
- CheckboxGPIO pins routed to test points for debugging
Status Indicators
- CheckboxPower LED on each major voltage railCritical
- CheckboxProgrammable status LEDs for firmware debugging
- CheckboxCommunication activity LEDs (if space permits)
- CheckboxError/fault indicators
8Manufacturing & BOM
Component Selection
- CheckboxAll components have manufacturer part number specifiedCritical
- CheckboxComponents in active production (not EOL/NRND)Critical
- CheckboxSecond-source alternatives identified for critical parts
- CheckboxFootprints verified against manufacturer drawings
- CheckboxThrough-hole vs SMD choice intentional
- CheckboxComponent temperature ratings match application
Supply Chain
- CheckboxStock availability verified for all componentsCritical
- CheckboxLead times acceptable for production schedule
- CheckboxMinimum order quantities acceptable
- CheckboxComponents available from authorized distributors
- CheckboxLong-lead items identified and ordered in advance
BOM Optimization
- CheckboxPassive values consolidated where possible (fewer unique values)
- CheckboxPackage sizes standardized (e.g., all 0402 or all 0603)
- CheckboxJLCPCB Basic parts used where possible (vs Extended)
- CheckboxSingle part number per value/size combination
- CheckboxBOM line count minimized for assembly cost reduction
9EMC & Compliance
EMI Prevention
- CheckboxSwitching regulator input filters prevent conducted EMI
- CheckboxClock signals shielded or filtered at board edge
- CheckboxHigh-speed signals not routed near connectors
- CheckboxSpread-spectrum clocking considered for EMI reduction
- CheckboxCrystal oscillators with low EMI characteristics selected
Filtering
- CheckboxPi filters on power inputs from external sources
- CheckboxCommon-mode chokes on differential signals leaving board
- CheckboxFerrite beads on power lines to sensitive circuits
- CheckboxFilter capacitors at connector pins
Grounding
- CheckboxSingle-point or multi-point grounding strategy definedCritical
- CheckboxAnalog and digital grounds connected at single point (if split)
- CheckboxChassis/earth ground connection point defined
- CheckboxGround plane continuity maintained under high-speed signals
- CheckboxReturn current paths considered for all signals
10Final Verification
DRC & ERC
- CheckboxERC (Electrical Rule Check) passes with no errorsCritical
- CheckboxDRC (Design Rule Check) passes with no errorsCritical
- CheckboxAll warnings reviewed and documented (waived or resolved)
- CheckboxUnconnected pins intentional and marked NC (No Connect)
- CheckboxAll nets named (no unnamed nets)
- CheckboxNo duplicate net names with different connections
Cross-Reference Check
- CheckboxErrata sheets reviewed for all major ICsCritical
- CheckboxApplication note circuits compared against reference designs
- CheckboxVendor FAE review for complex parts (if available)
- CheckboxEvaluation board schematics compared against design
- CheckboxPrevious revision issues verified as fixed
Peer Review
- CheckboxIndependent peer review completedCritical
- CheckboxFirmware engineer reviewed relevant sections
- CheckboxMechanical engineer verified physical constraints
- CheckboxTest engineer reviewed testability provisions
- CheckboxAll review findings documented and addressed
- CheckboxSign-off signatures obtained from all reviewers
Printable Checklist
This checklist is designed to be printer-friendly. Use your browser's print function (Ctrl/Cmd + P) to create a PDF or print a physical copy for your design review sessions.
Print Tips
- Select "Print backgrounds" to include category colors
- Use "Save as PDF" for a digital copy you can annotate
- Print double-sided to save paper
- Laminate for reuse with dry-erase markers
- Create custom versions by copying relevant sections
Pro Tip: Create a project-specific checklist by starting with this template and adding items specific to your product category (automotive, medical, industrial, consumer). Remove items that don't apply to streamline your review process.
Automated Review with Schemalyzer
While manual checklists are essential, automated tools can catch issues faster and more consistently. Schemalyzer analyzes your EasyEDA schematics automatically, checking for:
- Missing decoupling capacitors
- Unconnected pins that should be connected
- Power rail verification
- Component connection analysis
- Net naming consistency
- Signal path tracing
Try Schemalyzer Free
Upload your EasyEDA schematic JSON and get instant analysis with actionable recommendations.
Analyze Your SchematicConclusion
A thorough schematic review is one of the highest-ROI activities in electronics development. The 2-3 hours spent methodically going through this checklist can save weeks of debugging and thousands of dollars in PCB respins.
Remember that checklists are living documents. As you encounter new issues in your designs, add them to your personal checklist. Share learnings with your team to continuously improve your review process.
The best schematic review catches issues early, when fixes are cheap. The worst schematic review is the one that doesn't happen. Start using this checklist today, and watch your first-spin success rate improve dramatically.