Via Parameters
Typical: 0.2-0.6mm
1 oz ≈ 35µm
PCB thickness
Results
Single Via Thermal Resistance
192.4 °C/W
Vias Required
2
Total Thermal Resistance
96.21 °C/W
Temperature Rise
96.21 °C/W
Estimated Junction Temp
121.2 °C
Marginal - consider adding vias
Max Power Capacity
1.04 W
Suggested Via Array
Common Via Configurations
| Via Type | Via Diameter | Plating Thickness | R_th (°C/W) | Use Case |
|---|---|---|---|---|
| Small | 0.2 mm | 18 µm (0.5 oz) | ~280 | Signal vias, low power |
| Standard | 0.3 mm | 25 µm (0.7 oz) | ~140 | General thermal vias |
| Large | 0.4 mm | 35 µm (1 oz) | ~70 | Power devices |
| Power | 0.5 mm | 35 µm (1 oz) | ~50 | High power, LED |
| Filled | 0.6 mm | 50 µm (filled) | ~25 | Maximum thermal transfer |
Click on a row to use those values. R_th values are approximate for 1.6mm PCB thickness.
Understanding Thermal Vias
Thermal vias are plated through-holes in a PCB that transfer heat from one layer to another, typically from a component's thermal pad to an internal ground plane or bottom-side heatsink. They are essential for managing heat in power electronics, LED lighting, and high-performance circuits.
The thermal resistance of a via depends on its geometry and the copper plating thickness. Multiple vias in parallel reduce the total thermal resistance, improving heat dissipation.
Thermal Via Physics
Thermal Resistance Formula
The thermal resistance of a single via is calculated using Fourier's law of heat conduction:
Where:
- Rth = Thermal resistance (°C/W)
- L = Via length / PCB thickness (m)
- k = Thermal conductivity of copper = 385 W/(m·K)
- A = Cross-sectional area of copper annulus (m²)
Copper Annulus Area
For a standard plated via (not filled), the copper forms a hollow cylinder:
Where router is the via radius and rinner = router - plating thickness.
Parallel Via Calculation
When multiple vias are used in parallel, their thermal resistances add like parallel resistors:
Where N is the number of vias. This means doubling the vias halves the thermal resistance.
Design Guidelines
Via Placement
- Under the thermal pad — Place vias directly under exposed pads of QFN, DFN, and power packages
- Array pattern — Use a regular grid pattern for uniform heat distribution
- Via spacing — Minimum 0.5mm center-to-center for manufacturability
- Edge clearance — Keep vias at least 0.25mm from pad edges
Via Sizing
- Diameter — Larger vias have lower thermal resistance (0.3-0.5mm typical)
- Plating thickness — Thicker plating improves thermal conductivity (25-35µm typical)
- Filled vias — Copper or conductive epoxy filling provides best thermal performance
- Capped vias — Plated over to allow component placement on top
PCB Stack-up Considerations
- Ground plane proximity — Connect vias to a nearby ground plane for heat spreading
- Thermal relief — Avoid thermal reliefs on thermal pads if possible
- Bottom-side copper — Large copper pour on bottom improves convection
- Heatsink attachment — Consider mechanical heatsink for high power applications
Application Examples
QFN/DFN Packages
Most QFN packages have an exposed die attach pad (DAP) on the bottom. This pad requires thermal vias to transfer heat to internal copper layers. Typical designs use 4-9 vias depending on package size and power dissipation.
LED Thermal Management
High-power LEDs generate significant heat at the junction. Metal-core PCBs (MCPCB) or thermal via arrays under the LED thermal pad are essential. For 1W+ LEDs, expect to need 6-12 thermal vias or an MCPCB.
Power MOSFETs
DPAK and D2PAK packages dissipate heat through the drain tab. The tab should connect to a large copper pour with thermal vias to spread heat. Power dissipation over 2W typically requires additional thermal management.
Voltage Regulators
Linear regulators and switching converters generate heat proportional to their losses. Use the power dissipation calculator to determine heat generated, then size your thermal via array accordingly.
Frequently Asked Questions
Should I use filled vias or standard plated vias?
Filled vias provide better thermal conductivity but cost more. For most applications, standard plated vias with 25-35µm copper are sufficient. Use filled vias for high-power applications or when solder wicking is a concern.
How close can I place thermal vias?
Minimum spacing depends on your PCB manufacturer. Typically, 0.5mm center-to-center is achievable with standard processes. Check your fab's design rules for exact minimums.
Do thermal vias affect signal integrity?
Thermal vias are typically placed under component thermal pads, away from signal traces. If placed near high-speed signals, they can affect impedance. Keep thermal vias separate from signal routing areas.
Can I use thermal vias with solder paste?
Yes, but solder can wick through open vias causing voids. Options include: using smaller vias (<0.3mm), filled and capped vias, or tenting vias with solder mask. Some designs use via-in-pad with filled vias for best results.
How do I measure actual thermal performance?
Use a thermal camera or thermocouple to measure temperatures during operation. Compare measured junction temperature to calculated values. Actual performance may vary due to convection, radiation, and PCB-specific factors.